Methods and apparatus to reduce substrate voltage bounces and spike voltages in switching amplifiers

ABSTRACT

Methods and apparatus to reduce voltage bounces and spike voltages in switching amplifiers are disclosed. An example apparatus to reduce spike voltages in a switching amplifier disclosed herein comprises an input to sense an output voltage of the switching amplifier, and a pull-down circuit to electrically couple the apparatus with a transistor in the switching amplifier, wherein the pull-down circuit is configured to vary in strength based on the output voltage sensed by the input.

CROSS REFERENCE TO RELATED APPLICATIONS

This patent is a continuation-in-part of U.S. patent application Ser.No. 11/838,601, filed Aug. 6, 2007, which claims the benefit of U.S.Provisional Patent Applications bearing Ser. Nos. 60/822,030 and60/822,179, filed on Aug. 10, 2007 and Aug. 11, 2007, respectively. Allof the foregoing U.S. patent applications and U.S. Provisional PatentApplications are hereby incorporated by reference in their entireties.

FIELD OF THE DISCLOSURE

This disclosure relates generally to integrated circuits and, moreparticularly, to methods and apparatus to reduce substrate voltagebounces and spike voltages in switching amplifiers.

BACKGROUND

In recent years, the devices used to implement switching amplifiers haveincreased in performance, thereby improving audio fidelity. As the audiofidelity of switching amplifiers improves, switching amplifiers havebeen increasingly implemented in consumer electronics. Generally,switching amplifiers are high efficiency amplifiers that were initiallyused in electronic devices requiring power efficiency, such as mobilephones and other portable electronic devices.

However, switching amplifiers are increasingly being implemented instationary electronic devices such as home entertainment devices (e.g.,televisions, surround sound receivers, etc.). In such electronicdevices, the switching amplifiers are implemented to have higher poweroutput than switching amplifiers used in portable electronics. Forexample, switching amplifiers may be implemented in a high-fidelitysurround sound receiver having a total power output of hundreds ofwatts. In such cases, switching amplifiers may implemented in place oflinear amplifiers (e.g., a class A amplifier) because the large numberof amplifiers required (e.g., seven amplifiers for surround sound) andthe relatively low efficiency of class A amplifiers.

Furthermore, switching half-bridge amplifier circuits are commonly usedin the output stage(s) of many types of electronic amplifiers, such as,for example, class-D audio amplifiers. In a typical configuration, aswitching half-bridge amplifier, or output amplification stage, includesa high-side transistor and a low-side transistor. Field effecttransistors (FETs) are commonly used to implement half-bridgeamplifiers. In an example FET-based implementation, the output of thehalf-bridge amplifier is provided at the node at which the source of thehigh-side FET is coupled with the drain of the low-side FET.

During typical operation, the output of such a half-bridge amplifier isswitched between a high-side voltage substantially equal to the drainvoltage of the high-side FET and a low-side voltage substantially equalto the source voltage of the low-side FET. The output of the half-bridgeamplifier is switched to the high-side voltage by switching both thehigh-side FET ON and the low-side FET OFF. Conversely, the output of thehalf-bridge amplifier is switched to the low-side output voltage byswitching both the high-side FET OFF and the low-side FET ON. In otherwords, the high-side FET and the low-side FET are controlled in acomplimentary, yet opposite, fashion. In many switching half-bridgeamplifier implementations, transient spikes in the output voltage occurwhen the voltage output is switched from the high-side output voltage tothe low-side output voltage, and vice versa.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of an example switching amplifier.

FIG. 2 is an illustration of a protection device of the switchingamplifier of FIG. 1.

FIG. 3 is a cross section of a substrate implementing a switchingamplifier.

FIG. 4 is an illustration of another example switching amplifierimplementing a substrate current protector.

FIGS. 5A-5D illustrate cross sections of a substrate implementing theswitching amplifier of FIG. 4 at different stages during a deviceturn-on.

FIG. 6 is a cross section of a substrate implementing a substrate clamp.

FIG. 7 illustrates the doping profile of the substrate clamp of FIG. 6.

FIG. 8A illustrates a cross section of a substrate implementing anothersubstrate clamp.

FIG. 8B illustrates the doping profile of the substrate clamp of FIG.8A.

FIG. 8C illustrates the voltage drop of a substrate implementing thesubstrate clamp of FIG. 8A.

FIG. 9 illustrates a cross section of a substrate implementing anothersubstrate clamp.

FIG. 10 illustrates the voltage drop of a substrate implementing thesubstrate clamp of FIG. 9.

FIG. 11 is a block diagram of a first example half-bridge amplifiercircuit including example low-side and high-side spike reductioncircuits.

FIG. 12 is a block diagram of a second example half-bridge amplifiercircuit illustrating example implementations of the example low-side andhigh-side spike reduction circuits of FIG. 11.

FIG. 13 is a block diagram of an example full-bridge class-D amplifierimplemented using two of the example half-bridge amplifier circuits ofFIG. 11.

FIG. 14 is a flowchart representative of an example process that may beperformed to implement the example low-side spike reduction circuits ofFIGS. 11 and/or 12.

FIG. 15 is a flowchart representative of an example process that may beperformed to implement the example high-side spike reduction circuits ofFIGS. 11 and/or 12.

FIG. 16 is a block diagram of an example computer that may executeexample machine readable instructions used to implement some or all ofthe processes of FIGS. 15 and/or 16 to implement the example half-bridgeamplifiers of FIGS. 11 and/or 12, and/or the example full-bridge class-Damplifier of FIG. 13.

To clarify multiple layers and regions, the thickness of the layers areenlarged in the drawings. Wherever possible, the same reference numberswill be used throughout the drawing(s) and accompanying writtendescription to refer to the same or like parts. As used in this patent,stating that any part (e.g., a layer, film, area, or plate) is in anyway positioned on (e.g., positioned on, located on, disposed on, orformed on, etc.) another part, means that the referenced part is eitherin contact with the other part, or that the referenced part is above theother part with one or more intermediate part(s) located therebetween.Stating that any part is in contact with another part means that thereis no intermediate part between the two parts.

DETAILED DESCRIPTION

Methods and apparatus to reduce substrate voltage bounces and voltagespikes in switching amplifiers are disclosed herein with reference tocertain examples. As described herein, an integrated circuit is a die ora chip containing at least one active semiconductor device (e.g., an NPNtransistor, etc.). Thus, for example, an integrated circuit may containa single active device (e.g., a transistor) or the integrated circuitmay contain multiple active devices (e.g., a processor having millionsof transistors). Although the examples disclosed herein describe andaddress substrate bounce effects in switching amplifiers, the teachingsherein may be used in any device that suffers from substrate bounceeffects, or substrate currents due to parasitics associated with theintegrated circuit.

FIG. 1 is an illustration of an example switching amplifier 100 that maybe implemented into an electronics device (e.g., a cellular phone, astereo, etc.). Generally, the example switching amplifier 100 isimplemented on a silicon wafer (e.g., a P-type wafer, etc.) and packagedinto an integrated circuit that will be implemented into the electronicsdevice. The example switching amplifier 100 receives an input signal 102and a reference signal 104 at a pulse width modulator (PWM) 106. Usingthe reference signal 104 and the signal 102, the pulse width modulator106 forms a first PWM signal 112 and a second PWM signal 114. Personshaving ordinary skill in the art will readily appreciate that the PWMsignals 112, 114 are indicative of the power spectral density of signal102. As illustrated in the example of FIG. 1, the PWM signals 112, 114are complementary to each other.

The PWM signals 112, 114 are received by a protection device 116, whichincludes functionality to protect the example switching amplifier 100.For example, the protection device 116 may detect shorts, overheating,and so forth.

FIG. 2 illustrates the protection device 116 in more detail. In theexample of FIG. 2, the protection device 116 includes an over-currentprotector 202 to detect shorts, a temperature protector 204 to detectoverheating, and an under-voltage protector 206 to detect voltages.However, the protection device 116 may include any number of devices toprotect the switching amplifier 100 and its associated devices.

In the example of FIG. 1, the protection device 116 is further coupledto a first and second fault detectors 118 and 120. In the example ofFIG. 1, the fault detectors 118, 120 sense the current in the switchingamplifier 100 to determine if there is an over-current condition (i.e.,the current exceeds a predetermined limit). The fault detectors 118, 120communicate with the over-current protector 202 to indicate anover-current condition. The protection device 116 also conveys the PWMsignal 112 to a first gate driver 122 and the PWM signal 114 to a secondgate driver 124. The gate drivers 122, 124 are both coupled with avoltage source VSS 126. The gate drivers 122, 124 are also coupled to afirst and second switch 128 and 130, respectively.

The gate drivers 122, 124 amplify the PWM signals 112, 114 to drive theswitches 128, 130, respectively. In the example of FIG. 1, the switches128, 130 are implemented by lightly doped metal oxide semiconductorfield effect transistors (LDMOS). The LDMOS devices are implemented inthe switching amplifier 100 to handle the high switching frequency ofthe PWM signals 112, 114. However, the switches 128, 130 may beimplemented by any suitable device (e.g., NPN transistors, etc.).

In the example of FIG. 1, the drain of the LDMOS device 128 is coupledto a voltage source VDD 140. The fault detector 118 senses the currentflowing between the LDMOS device 128 and the voltage source 140. Thesource of the LDMOS device 130 is coupled to ground 144 (e.g., a lowvoltage source, etc.). The fault detector 120 senses the current flowingbetween the LDMOS device 130 and the ground 144. The source of LDMOSdevices 128 and the drain of LDMOS device 130 are both coupled togetherand further coupled to a playback device 152 (e.g., a speaker, etc.) viaa filter 150.

As described above, the drivers 122, 124 amplify the PWM signals 112,114, to drive the LDMOS 128, 130 devices, respectively. The LDMOSdevices 128, 130 rapidly turn on and off based on the voltage of the PWMsignals 112, 114. In other words, the LDMOS devices 128, 130 reproducethe PWM signals 112, 114 via their respective sources. However, the PWMsignal 114 provided via the LDMOS device 130 will be inverted (i.e., thevoltage will be negative). The PWM signals 112, 114 are then summed atthe source of the LDMOS devices 128, 130. The summed PWM signal isconveyed to the playback device 152 via the filter 150, which filtersthe summed PWM signal to form the output signal.

In some examples, when the LDMOS device 128 is turned on, current flowsinto the filter 150 via the LDMOS device 128. However, the filter 150may store energy (e.g., by having an inductor or capacitor). As aresult, when the LDMOS device 128 is turned off and the LMDOS device 130is turned on, the LDMOS device 130 draws current from the filter 150 tocause the output signal to have a negative voltage swing. Afterfiltering, the output signal is substantially similar to the inputsignal 102 (i.e., the output signal is audibly similar to the inputsignal 102), however, the output signal has more power. The outputsignal is received by the playback device 152, which audibly presentsthe output signal to a listener. Thus, the switching amplifier 100 is ahigh fidelity amplifier that reproduces the input signal to audiblypresent to the listener.

In addition, the voltage source 126 is coupled with a voltage regulator132. The voltage regulator 132 is also coupled to a voltage reference128, which is a voltage reference (e.g., a bandgap reference) that isgenerated within the switching amplifier 100 (i.e., the voltagereference is generated in the integrated circuit). Using the voltagereference 128, the voltage regulator 132 outputs a regulated voltage(e.g., 3.3 volts) for the protection device 116. In addition, the outputof the voltage regulator 132 is coupled to ground 136 via a capacitor134. In the example of FIG. 1, the capacitor 134 stores a voltage (e.g.,3.3 volts) and sources additional current to the protection device 116when the voltage regulator 132 cannot supply enough current to theswitching amplifier 100. Thus, the capacitor 134 is configured to storeenergy (e.g., a tank) for the operation of the switching amplifier 100.

In the example of FIG. 2, the over-current protector 202 may beimplemented by any suitable device (e.g., a processor, a logic circuit,etc.) having a memory 208. In such examples, the memory 208 is generallya volatile memory, however, the memory 208 may be implemented by anytype of memory (e.g., flash memory, registers in a processor, etc.).Generally, in a switching amplifier 100, the current output from theswitching amplifier 100 increases and decreases rapidly based on theinput signal 102. In such examples, one method to determine if there isa short in the switching amplifier 100 is to count the number of timesthe current in the LDMOS devices 128, 130 exceed a predetermined currentlimit.

In some examples, the over-current protector 202 implements a counter210 in the memory 208 to count the number of times the current passedthrough LDMOS devices 128, 130 exceed a threshold within a predeterminedtime period (e.g., 10 milliseconds) based on input from fault detectors118, 120, which determine if the current flowing via either of the LDMOSdevices 128, 130 exceed a current limit (e.g., 30 amps). In the eventthat the current through the LDMOS devices 128, 130 exceeds the currentlimit, the fault detector that detects the current communicates a signalto the over-current protector 202 to indicate an over-current condition.The over-current protector 202 receives the signal and, as a result,increments the counter 210 and stores it in memory 208. Afterincrementing the counter 210, the over-current protector 202 comparesthe counter 210 with a predetermined value that may be indicative of anover-current condition (e.g., 15). If the counter 210 exceeds thepredetermined value, the over-current protector 202 disables theswitching amplifier 100 by, for example, interrupting the PWM signalsfrom being coupled to the drivers 122,124 to protect the switchingamplifier 100 and its associated devices (e.g., the playback device152).

In some examples, the LMDOS devices 128, 130 are high power devicescapable of handling large currents (e.g., over 25 amps). In the exampleof FIG. 1, parasitics (e.g., capacitance, etc.) associated with theLDMOS devices 128, 130 may cause current to leak into the substrate ofthe silicon wafer. FIG. 3 illustrates a cross-sectional view of asubstrate 300 that may implement the switching amplifier 100. In theexample of FIG. 3, the substrate 300 is implemented by a P-type siliconwafer. However, the substrate 300 may be implemented by any suitablematerial (e.g., silicon germanium, silicon, gallium arsenide, galliumnitride, etc.).

FIG. 3 also illustrates a cross-section of the LDMOS device 130. In theexample of FIG. 3, the LDMOS device 130 is a simplified illustration ofan LDMOS device and is included to show its associated parasitics andcurrents. The LDMOS device 130 is formed in an N-well 301 disposed inthe substrate 300 that includes a P-well 302 disposed within the N-well301. An N-buried layer 303 rests below the N-well 301. The N-buriedlayer 303 isolates the devices formed above or within the N-buried layer322 from parasitics, noise, and other effects from devices of thesubstrate 300.

A first N-well 304 (i.e., a silicon region that is implanted with N-typeions to make the region an N-type region) is disposed in the P-well 303.A pad 306 (e.g., a poly-silicon pad, a metal, etc.) is in contact withthe N-well 304. A second N-well 308 is also disposed in the substrate300 and in contact with the N-buried layer 303. The N-well 308 alsoincludes a pad 310 in contact with the N-well 308. An oxide layer 312 isplaced on the top surface of the substrate 300 and is disposed betweenthe N-wells 304, 308. A pad 314 (e.g., a poly-silicon, etc.) is incontact with the oxide layer 312 to form the gate of the LDMOS device128. In the example of FIG. 3, the pad 310 forms the drain of the LDMOSdevice 128 and the pad 306 forms the source of the LDMOS device 128. Inaddition, the bottom surface of the substrate 300 is coupled to a lowvoltage source (e.g., the ground 144, etc.).

The example of FIG. 3 also includes a device disposed in the substrate300 via a complementary metal oxide semiconductor (CMOS) process, whichforms N-channel devices and P-channel devices in the substrate 300. Onesuch device that may disposed in the substrate 300 is the over-currentprotector 202, however, any device may be placed in the substrate (e.g.,logic, etc.). In the example of FIG. 3, the over-current protector 202is isolated from devices by placing a deep N-buried layer 322 disposedin the substrate 300. A deep N-well 324 is disposed above the N-buriedlayer 322 and a P-well 326 and an N-well 328 are disposed within theN-well 324. In the example of FIG. 3, the N-well 328 implements theP-channel devices (not shown) of the over-current protector 202 and theP-well implements the N-channel devices (not shown) of the over-currentprotector 202. The devices of the P-well 326 are in contact at least onepad 332 and the devices of the N-well 328 are in contact with at leastone pad 330.

The P-well 326 is coupled to the ground 136 via any suitable device(e.g., a bond wire, etc.) and the N-well 328 is coupled to the capacitor134 via any suitable device (e.g., a bond wire, a metal trace, etc.).The capacitor 134 is further coupled to ground 136. Ideally, the N-well328 is coupled via a path without any parasitics. However, because thecapacitor 134 is located on the circuit board, a parasitic inductor 334is included in the example of FIG. 3 to illustrate an inductance (e.g.,5 nH) between the capacitor 134 and the N-well 328. Similarly, theP-well 326 includes a parasitic inductor 336 (e.g., 5 nH).

As described above, the voltage regulator 132 outputs a voltage and thecapacitor 134 stores charge to supply to the voltage regulator 132 whenthere is large demand for current. As illustrated in the example of FIG.3, the capacitor 134 is coupled to the pad 330 of the N-well 328. Thecontact 332 of the P-well 326 is coupled to the analog ground 136 (e.g.,a chip level ground, etc.) via any suitable connector (e.g., a bondwire, a pad, etc.).

Generally, the devices disposed in the substrate 300 include manyparasitic effects that may or may not affect the switching amplifier100. For example, in the example of FIG. 3, due to the P-type substrate300 and N-buried layer 322, a parasitic p-n junction exists between theP-type substrate 300 and the N-buried layer 322. Thus, a diode 340 isincluded in the example of FIG. 3 to illustrate the parasitic diodeformed by the P-type substrate 200 and the N-buried layer 222. Normally,the diode 340 is reverse biased to isolate devices of the substrate 300.Still, in other examples, the LDMOS device 130 includes a parasitic p-njunction represented by a diode 342 is formed between the N-well 308 andthe P-well 302 and a parasitic p-n junction represented by a diode 344,which is formed between the N-well 308 and the P-type substrate 300.Thus, in some examples, current may flow from the P-regions (e.g., theP-type substrate 300, the P-well 302, etc.) into the N-well 308.

In the example of FIG. 1, when the LDMOS device 130 is turned off andthe LDMOS 128 is transitioning to a high state (e.g., turning on), dueto the stored energy in the filter 150, a small amount of current mayleak in the drain of the LDMOS device 130 due to the parasitic diodes342, 344. In such a case, the drain of LDMOS device 130 has a negativevoltage due to the parasitic current flowing via its drain. As the LDMOSdevice 128 turns on and drives the voltage at the drain of the LMDOSdevice 130 high, minority charge carriers injected into the substrate300 via the N-well 308 and the N-buried layer 303 are swept back acrossthe junction. At the same time, LDMOS device 128 is conducting a largecurrent into the playback device 152 via the filter 150. At the sametime, for a brief moment, current from LMDOS device 128 may be injectedinto the substrate 300, thereby forming a substrate current 318. In someexamples, the substrate current 318 may be a significant current (e.g.,4 amps).

The substrate current 318 disperses and seeks the path of leastimpedance (i.e., resistance) to a low voltage source (e.g., ground 136,ground 144, etc.). However, in some examples, the substrate current 318may flow into ground 136 via the over-current protector 202. Asdescribed above, there is a parasitic diode 340 between the P-typesubstrate 300 and the N-buried layer 322, which can pass the substratecurrent 318 to ground 136. In such examples, the voltage of thesubstrate 300 must be larger than the voltage of the N-well 328 due tothe voltage drop from the diode 340. Thus, the voltage of the substrate300 is the voltage of the N-well 328 summed with the voltage drop of thediode 340 (e.g., 0.7 volts). In some examples, the voltage of the N-well328 is larger than the voltage of the capacitor 134 due to the parasiticinductance 334 (e.g., 3.6 volts). As a result of the substrate current318 flowing in the substrate 300, the diode 340 becomes forward biasedand causes the substrate 300 to have a positive voltage (e.g., 4.3volts). In such a case, because the substrate current 318 is brief induration, the substrate current 318 will flow across the diode 340 andthen into ground 136 via the capacitor 134.

After the charge carriers are removed from the substrate 300, thesubstrate current 318 diminishes (i.e., there is no more substratecurrent 318 or the substrate current 318 is negligible). As a result,there is no current in the substrate 300 to forward bias the diode 340.Persons having ordinary skill in the art will readily appreciate thatcharge carriers injected into the N-buried layer 322 during forward biasare removed across the junction between the N-buried layer 322 and thesubstrate 300, thereby causing a negative current to flow across thediode 340 and causing the substrate 300 to have a low voltage (i.e.,reverse recovery). Thus, the voltage of the N-well 328 is substantiallyreduced (e.g., to zero volts) for a brief moment while the diode 340recovers. Due to the low voltage difference between the N-well 328 andthe P-well 326, the voltage output by the voltage regulator 132 dropsbelow the minimum threshold voltage.

As described above, the over-current protector 202 includes a memory 208to store the number of over-current conditions that have occurred.Generally, the memory 208 must be held to a minimum voltage (e.g., 1.5volts) to store the values contained therein. In the example of FIG. 1,the voltage regulator 132 supplies the voltage to the memory 208.However, as described above, substrate current 318 causes the voltageregulator 132 to briefly drop in voltage during low-to-high transitionsof the LDMOS device 128. As a result, the voltage of the voltageregulator 132 may drop below the minimum threshold voltage (e.g., 1.5volts), thereby turning off the memory 208 and clearing its contents(i.e., values, instructions, etc.). Thus, the memory 208 of theover-current protector 202 is reset, thereby clearing the value of thecounter 210 and preventing the over-current protector 202 from detectingover-current conditions.

In other words, the low-to-high transitions of the LDMOS device 128 maycause the LDMOS device 130 to inject a substrate current into thesubstrate 300 and cause the over-current protector 202 to briefly dropin voltage, thereby preventing the over-current protector 202 fromdetecting over-current conditions. In such a case, because theover-current protector 202 cannot properly count over-current conditionsin the LDMOS devices 128, 130, the over-current protector 202 cannotdetect short circuits, which may lead to damage to the switchingamplifier 100 and its associated devices (e.g., playback device 152).

FIG. 4 illustrates the example switching amplifier 100 implementing asubstrate current protector 402. The substrate current protector 402 isimplemented by floating the capacitor 134 (i.e., not connected to anindependent node such as a ground or voltage source) and coupling thecapacitor 134 to ground 136 via the substrate current protector 402,which is implemented by a resistor having a low resistance (e.g., 3.3ohms). In other words, the protection device 116, which receives voltagefrom the voltage regulator 132, is coupled to ground via the capacitor134 and the resistor 402.

FIGS. 5A-5D illustrates a cross section view of the substrate 300 thatimplements the switching amplifier 100 coupled to the resistor 402. Inthe examples of FIGS. 5A-5D, different stages of the over-currentprotector 202 are illustrated when the LDMOS device 130 injects thesubstrate current 318. As illustrated in FIG. 5A, the P-well 326 iscoupled to ground 136 via the resistor 402. Similarly, N-well 328 iscoupled to ground via the capacitor 134 and the resistor 402. Inaddition, the N-well 328 is coupled to the voltage regulator 132 andreceives a regulated voltage.

Initially, as illustrated in the example of FIG. 5A, the LDMOS device130 is turned off and the voltage regulator 132 supplies voltage (e.g.,3.3 volts) to the over-current protector 202. Initially, no currentflows from the P-well 326 to ground via the resistor 402, thus theP-well 326 has a voltage of zero volts. At the same time, the voltageapplied to the N-well 328 is the regulated voltage (e.g., 3.3 volts).

As illustrating in FIG. 5B, when the LDMOS device 128 turns on andcauses the LDMOS device 130 to inject the substrate current 318, thesubstrate current 318 flows into the substrate 300 and forward biasesthe diode 340. In such a case, the substrate current 318 will flowacross the capacitor 134 and into the resistor 402, creating a voltageacross the resistor 402 (e.g., 1.5 volts). Due to the voltage betweenthe resistor 402 and the capacitor 134, the voltage at the capacitor 134increases (e.g., 4.8 volts). In some examples, the parasitic inductance334 causes the voltage of the N-well 328 to be higher (e.g., 5.1 volts).As a result of the substrate current 318 flowing via the diode 340, thesubstrate 300 has a higher voltage than the N-well 328 (e.g., 5.8volts).

In the example of FIG. 5C, when charge carriers of the parasitic diodes342, 344 of the LDMOS device 130 are swept back across their respectivejunctions, the substrate current 318 diminishes and cannot forward biasthe diode 340. However, as described above, the reverse recovery of thediode 340 creates a negative voltage and reduces the voltage of theN-well 328 (e.g., to zero volts). The negative current is provided viaground 136, thereby creating a negative voltage across the resistor 402and at the P-well 326 (e.g., to −1.5 volts). The voltage of thecapacitor 134 is also reduced based on its voltage (e.g., to 1.8 volts).However, the voltage of the N-well 328 is reduced (e.g., to zero volts),but the difference in the voltages between the P-well 326 and the N-well328 (e.g., 1.5 volts) cause the over-current protector 202 to maintain avoltage that exceeds the minimum threshold voltage. Thus, by floatingboth the capacitor 134 and the P-well 326, the resistor 402 prevents thevoltage of the voltage regulator 132 from falling below the minimumthreshold value. As a result, the resistor 402 prevents the memory 208from clearing due to the substrate current 318 injected via the LDMOSdevice 130. After the diode 340 has recovered, the over-currentprotector 202 returns to its normal voltage (e.g., 3.3 volts) as shownin the example of FIG. 5D.

Another method to reduce the effects of the substrate current is toprovide a path to ground to minimize the substrate current flowing inthe substrate 300. In the example of FIG. 6, a substrate clamp 600clamps portions of the substrate 300 to ground 144, thereby providing apath for the substrate current 318 to escape the substrate 300. FIG. 6illustrates a substrate 300 implementing a substrate clamp 600 via aP-well 602 in contact with a pad 604, which is coupled to ground 144. Asreadily appreciated by persons having skill in the art, P-wells areformed by injecting ions (e.g., boron) into the silicon, thus freeingholes of the silicon to carry energy.

FIG. 7 illustrates an example doping profile of the P-well 602. In theexample of FIG. 7, the P-well has a lightly doped region 702 and aheavily doped region 704. Persons of ordinary skill in the art willreadily recognize that the lightly doped region 702 has a largerresistance than the heavily doped region 704. In the example of FIG. 7,the lightly doped region 702 enables high voltage operation of thedevices on the substrate 300. As a result, the resistive path of thelightly doped region 702 presents an impedance to the substratecurrents, thereby reducing the amount of substrate current flowing fromthe substrate 300 via the P-well 602. The substrate current 318 choosesthe easiest path to ground 144, thus the substrate current 318 exits viathe over-current protector 202 and causes the over-current protector 202to drop in voltage as explained in conjunction with FIG. 3.

FIG. 8A illustrates substrate 300 implementing another substrate clamp800 constructed differently from the substrate clamp 600 of FIG. 6. Thesubstrate clamp 800 includes an N-well 802, a deep-N well 804, and anN-buried layer 806. In the example of FIG. 8, the deep N-well 804 isdisposed in the substrate 300 and the N-well 802 is disposed in the deepN-well 804. The N-buried layer 806 is disposed in the substrate 300below the deep N-well 804. A pad 808 is also in contact with the N-well802. The N-well 802 is coupled to ground 144 to a P-well 810 via anysuitable means (e.g., bond wires, plating, etc.). The P-well 810 is incontact with a pad 812 to connect to devices outside of the substrate300 (e.g., ground, voltage sources, etc.). In the example of FIG. 8, thesubstrate clamp 800 and the P-well 810 are coupled to ground 144 via aparasitic inductance 816 (e.g., 5 nH).

FIG. 8B illustrates a graph showing the doping profile of the substrateclamp 800. As illustrated in FIG. 8B, the substrate clamp 800 is heavilydoped, thereby having a low impedance when current travels through it.As described above, when substrate currents flow into the substrate 300,a parasitic diode 814 is formed via the p-type substrate 300 and theN-buried layer 806. However, by forward biasing the parasitic diode 814,the substrate current 318 forms a low impedance path to ground 144 viathe substrate clamp 800. Thus, the substrate 800 has a voltage, but dueto the low impedance of the substrate clamp 800, the voltage of thesubstrate 300 is reduced. In addition, the voltage of the substrate 300is not uniform, thereby substantially isolating the over-currentprotector 202 from the substrate current 318. Thus, the substrate clamp800 substantially removes the substrate current 318 and substantiallyreduces the substrate voltage.

FIG. 8C illustrates a graph of the voltage of the over-current protector202 with the substrate clamp 800 coupled to the P-well 810 via theparasitic inductance 816. As described above, most substrate current 318escapes via the substrate clamp 800. However, during a low-to-hightransition, the voltage of the over-current protector 202 is pulled downvia the substrate current escaping via the over-current protector 202.In the example of FIG. 8A, the voltage of the voltage regulator 132remains above a minimum voltage threshold (e.g., 1.5 volts) to allow thememory 208 to store the counter 210 associated with the over-currentprotector 202.

FIG. 9 illustrates an example substrate clamp 800 implementing a secondP-well 902 having a pad 904. The second P-well 902 is coupled to ground144 and the substrate clamp 800. In the example of FIG. 9, the P-well902 is coupled to ground 144 via parasitic inductance 906. However, theparasitic inductances 906, 816 are connected in parallel. By placing theparasitic inductances 906, 816 in parallel, the total inductance betweenthe substrate clamp 800 and ground 144 decreases. The substrate clamp800 thereby presents a lower impedance to the substrate current 318.FIG. 10 illustrates a graph showing the voltage of the over-currentprotector 202 during a low-to-high transition of the LDMOS device 128that causes LDMOS device 130 to inject the substrate current 318.However, in the example of FIG. 10, the substrate clamp 800 is connectedto ground 144 via a lower inductance (e.g., 1.2 nH). As a result, moresubstrate current flows out via the substrate clamp 800, therebydecreasing the substrate current 318 flowing via the over-currentprotector 202. As illustrated in the example of FIG. 10, the voltagedrop due to the substrate current 318 is decreased due to the lowerimpedance between the substrate clamp 800 and ground 144.

Focusing next on voltage spike reduction, a block diagram of a firstexample switching half-bridge amplifier circuit 1100 implementingvoltage spike reduction according to the methods and/or apparatusdescribed herein is illustrated in FIG. 11. The first example switchinghalf-bridge amplifier circuit 1100 includes an output stage 1105providing a voltage output 1110 for the amplifier circuit 1100. Theexample output stage 1105 includes a high-side transistor 1115 and alow-side transistor 1120. In the illustrated example, the high-sidetransistor 1115 and the low-side transistor 1120 are implemented as ahigh-side field effect transistor (FET) 1115 and a low-side FET 1120. Ofcourse, other types of transistors could be used to implement thehigh-side transistor 1115 and the low-side transistor 1120. The voltageoutput 1110 in the illustrated example is provided by the node at whichthe source of the high-side FET 1115 is coupled with the drain of thelow-side FET 1120. The drain of the high-side FET 1115 is coupled to ahigh-side voltage input 1125, such as, for example, PVDD 1125 as shownin FIG. 11. The source of the low-side FET 1120 is coupled to a low-sidepower voltage input 1130, such as, for example, PGND 1130 as shown.

To control operation of the high-side FET 1115 and the low-side FET1120, the first example switching half-bridge amplifier circuit 1100includes respective high-side and low-side drivers 1135 and 1140. Thelow-side driver 1140 is powered by a low-side gate power input 1145,such as, for example, GVDD 1145 as shown in FIG. 11. The high-sidedriver 1135 is powered by a high-side gate power input 1150, such as,for example, a bootstrap power input BST 1150 as shown.

The example high-side driver 1135 is coupled to a high-side controlinput 1155 used to control whether the high-side FET 1115 is switched ONor OFF. In the illustrated example, the high-side driver 1135 isconfigured to generate an output control voltage to turn ON thehigh-side FET 1115 when the high-side control input 1155 is set to alogic HIGH value, and to turn OFF the high-side FET 1115 when thehigh-side control input 1155 is set to a logic LOW value. Similarly, theexample low-side driver 1140 is coupled to a low-side control input 1160used to control whether the low-side FET 1120 is switched ON or OFF. Inthe illustrated example, the low-side driver 1140 is configured togenerate an output control voltage to turn ON the low-side FET 1120 whenthe low-side control input 1160 is set to a logic HIGH value, and toturn OFF the low-side FET 1120 when the low-side control input 1160 isset to a logic LOW value.

The example switching half-bridge amplifier circuit 1100 furtherincludes a high-side spike reduction circuit 1165 to electrically couplethe control output of the high-side driver 1135 to the gate input of thehigh-side FET 1115. Similarly, the example amplifier circuit 1110includes a low-side spike reduction circuit 1170 to electrically couplethe control output of the low-side driver 1140 to the gate input of thelow-side FET 1120. In the illustrated example, both the high-side spikereduction circuit 1165 and the low-side spike reduction circuit 1170 areconfigured to provide variable pull-down strengths to the gate inputs ofthe high-side FET 1115 and the low-side FET 1120, respectively. Inparticular, the spike reduction circuits 1165 and 1170 vary theirrespective pull-down strengths based on the sensed output voltage at thevoltage output 1110 of the example amplifier circuit 1100.

Generally, a pull-down circuit (e.g., such as a pull-down resistor) isprovided at an input of a transistor (e.g., such as the FETs 1115 and/or1120) to provide a stable low voltage reference when the transistorinput (e.g., gate input) is set to turn the transistor OFF. The strengthof the implemented pull-down circuit is usually chosen as a compromisebetween increasing transistor switching speed and reducing transistoroutput voltage spikes. For example, a high pull-down strength (e.g., alow pull-down resistance) typically results in a fast transistor turnOFF and lower power dissipation and idle current, but at the expense ofincreased transient spikes in the transistor output voltage. Conversely,a low pull-down strength (e.g., a high pull-down resistance) typicallyresults in decreased transient spikes in the transistor output voltage,but at the expense of a slower transistor turn OFF and higher powerdissipation and idle current.

As described below in detail, the spike reduction circuits 1165 and1170, however, are configured to vary their respective pull-downstrengths to enable fast transistor turn OFF times while reducingtransient output voltage spikes, power consumption and idle currents. Inparticular, the example spike reduction circuits 1165 and 1170 bothprovide a higher pull-down strength when initially turning OFF an outputstage transistor, and then reduce the pull-down strength as thetransistor transitions to a fully OFF state. Turning to the examplelow-side spike reduction circuit 1170, when the low-side FET 1120 isswitched from ON to OFF by the low-side driver 1140 (and the high-sideFET 1115 is switched from OFF to ON in a complimentary fashion atsubstantially the same time, for example, such as within approximately15 nanoseconds (ns) of the low-side FET 1120 being switched from ON toOFF), the low-side spike reduction circuit 1170 initially provides ahigh pull-down strength to the gate input of the low-side FET 1120. Thishigh pull-down strength enables initially fast switching of the low-sideFET 1120 from ON to OFF. Then, as the output voltage at the voltageoutput 1110 increases (e.g., such as due to the high-side FET 1115 beingswitched ON while the low-side FET 1120 is being switched OFF, a loadcurrent being forced into the voltage output 1110 when the low-side FET1120 is being switched OFF, etc.), the low-side spike reduction circuit1170 senses this increase in output voltage. When the output voltage atthe voltage output 1110 reaches a predetermined value, the examplelow-side spike reduction circuit 1170 reduces the pull-down strengthprovided to the gate input of the low-side FET 11120. This reducedpull-down strength results in lower transient voltage spikes at thevoltage output 1110 as the low-side FET 1120 reaches its fully OFFstate.

The example high-side spike reduction circuit 1165 operates in a mannersimilar to the example low-side spike reduction circuit 1170. Inparticular, turning to the example high-side spike reduction circuit1165, when the high-side FET 1115 is switched from ON to OFF by thehigh-side driver 1135 (and the low-side FET 1120 is switched from OFF toON in a complimentary fashion at substantially the same time, forexample, such as within approximately 15 nanoseconds (ns) of thehigh-side FET 1115 being switched from ON to OFF), the high-side spikereduction circuit 1165 initially provides a high pull-down strength tothe gate input of the high-side FET 1115. This high pull-down strengthenables initially fast switching of the high-side FET 1115 from ON toOFF. Then, as the output voltage at the voltage output 1110 decreases(due to the low-side FET 1120 being switched ON while the high-side FET1115 is being switched OFF), the high-side spike reduction circuit 1165senses this decrease in output voltage. When the output voltage at thevoltage output 1110 reaches a predetermined value, the example high-sidespike reduction circuit 1165 reduces the pull-down strength provided tothe gate input of the high-side FET 1115. This reduced pull-downstrength results in lower transient voltage spikes at the voltage output1110 as the high-side FET 1115 reaches its fully OFF state.

A block diagram of a second example half-bridge amplifier circuit 1200that implements voltage spike reduction according to the methods and/orapparatus described herein is illustrated in FIG. 12. The second examplehalf-bridge amplifier circuit 1200 provides more detailed exampleimplementations of the example spike reduction circuits 1165 and 1170included in the first example switching half-bridge amplifier circuit ofFIG. 11. As such, like elements in FIGS. 11 and 12 are labeled with thesame reference numerals. For brevity, the detailed descriptions of theselike elements are provided above in connection with the discussion ofFIG. 1 and, therefore, are not repeated in the discussion of FIG. 12.

Similar to the first example circuit 1100 of FIG. 11, the second exampleswitching half-bridge amplifier circuit 1200 of FIG. 12 includes theoutput stage 1105 providing the voltage output 1110, the high-side andlow-side FETs 1115 and 1120, the high-side and low-side drivers 1135 and1140 with their respective high-side and low-side control inputs 1155and 1160, and the high-side and low-side spike reduction circuits 1165and 1170.

Turning first to the example low-side spike reduction circuit 1170, theexample implementation of this circuit as illustrated in FIG. 12includes a low-side pull-down circuit 1204 configured to be coupled withthe gate input of the low-side FET 1120. The low-side pull-down circuit1204 provides a stable voltage reference for the gate input when thegate input is set to turn OFF the low-side FET 1120. The low-side spikereduction circuit 1170 in the illustrated example also includes apull-up transistor 1208 implemented as, for example, a pull-up FET 1208.The pull-up FET 1208 implements a pull-up circuit configured to becoupled with the gate input of the low-side FET 1120. The pull-up FET1208 provides a stable voltage reference for the gate input when thegate input is set to turn ON the low-side FET 1120.

The example low-side pull-down circuit 1204 includes a first pull-downtransistor 1212 and a second pull-down transistor 1216. In theillustrated example, the first pull-down transistor 1212 and the secondpull-down transistor 1216 are implemented, respectively, as a firstpull-down FET 1212 and a second pull-down FET 1216. The first and secondpull-down FETs 1212 and 1216 of the illustrated example are configuredto allow the strength of the low-side pull-down circuit 1204 to varybased on the output voltage sensed at the voltage output 1110. Inparticular, the first and second pull-down FETs 1212 and 1216 provide ahigh pull-down strength (e.g., corresponding to a low resistance path toPGND 1130) for the low-side pull-down circuit 1204 when both FETs areinitially turned ON. As discussed above in connection with FIG. 11, thishigh pull-down strength causes the low-side FET 1120 to begin switchingrapidly to the OFF state. Then, at a later time when the output voltage1110 increases by a predetermined amount, the second pull-down FET 1216is turned OFF to reduce the pull-down strength (e.g., corresponding to ahigher resistance path to PGND 1130) for the low-side pull-down circuit1204. As discussed above in connection with FIG. 11, this lowerpull-down strength causes a reduction in the voltage spikes observed atthe output of the low-side FET 1120 and, thus, at the voltage output1110.

The second pull-down FET 1216 included in the example low-side pull-downcircuit 1204 is controlled by the remaining circuitry in the examplelow-side spike reduction circuit 1170 as follows. As a startingreference point, the low-side FET 1120 is assumed to be ON and thehigh-side FET 1115 is assumed to be OFF, resulting the output voltage1110 being substantially equal to the voltage at PGND 1130. For thelow-side FET 1120 to be turned ON, the low-side control input 1160 willbe set to a logic HIGH value, resulting in a logic LOW value at theoutput of the low-side driver 1140. A logic LOW value at the output ofthe low-side driver 1140 causes the pull-up FET 1208 to turn ON and topull up the gate input of the low-side FET 1120 to a voltagesubstantially equal to the voltage at GVDD 1145, thereby turning ON thelow-side FET 11120.

Next, assume that a logic LOW value is applied to the low-side controlinput 1160 to turn OFF the low-side FET 1129. This results in a logicHIGH value at the output of the low-side driver 1140, thereby causingthe pull-up FET 1208 to turn OFF. Additionally, the logic HIGH value atthe output of the low-side driver 1140 causes the first and secondpull-down FETs 1212 and 1216 to turn ON. When the first and secondpull-down FETs 1212 and 1216 are turned ON, the gate input of thelow-side FET 1120 is pulled down to a voltage substantially equal to thevoltage at PGND 1130, thereby causing the low-side FET 1120 to beginturning OFF. During normal operation, the high-side FET 1115 will beturned ON at approximately the same time that the low-side FET 1120 isturned OFF, for example, such as within approximately 15 nanoseconds(ns) of the low-side FET 1120 being turned OFF. Thus, when the low-sideFET 1120 begins turning OFF, the voltage at the voltage output 1110 willbegin increasing to a value substantially equal to the voltage at PVDD1125.

The low-side spike reduction circuit 1170 includes inputs 1220 and 1224to sense the voltage at voltage output 1110 and, in particular, thevoltage at the voltage output 1110 relative to the other side of thelow-side FET 1120. In the illustrated example, the input 1220 iselectrically coupled to the cathode of a Zener diode 1228 and the inputto 1224 is electrically coupled to the anode of the Zener diode 1228.More specifically, the input 1224 is electrically coupled to the anodeof the Zener diode 1228 through a first bias resistor 1232, a biastransistor 1236 and a second bias resistor 1240. In the illustratedexample, the bias transistor 1236 is implemented as a bias FET 1236whose gate input is coupled to GVDD 1145. When the low-side FET 1120 isinitially turned OFF after being in the ON state, the voltage at thevoltage output 1110 and, thus, at the input 1220 will still besubstantially equal to the voltage at PGND 1130. Thus, no current willinitially flow through the Zener diode 1228 because it will be onlynominally reverse-biased.

With no current initially flowing through the Zener diode 1228, nocurrent will flow through the bias FET 1236 and its source, therefore,will have a voltage substantially equal to PGND 1130 (tied through thefirst bias resistor 1232). As a result, the source of the bias FET 1236will provide a logic LOW value to the input of an inverter 1244 whichwill, in turn, provide a logic HIGH value to one input of an AND gate1248. When the logic LOW value is applied to the low-side control input1160 to turn OFF the low side FET 1120, the low-side driver 1140 willprovide a logic HIGH value to the other input of the AND gate 1248. Withboth inputs set to logic HIGH, the output of the AND gate 1248 will be alogic HIGH, thereby turning ON the second pull-down FET 1216. The firstpull-down FET 1212 will also be turned ON by the logic HIGH output ofthe low-side driver 1140. With both pull-down FETs 1212 and 1216initially turned ON when the low-side FET 1120 is initially configuredto turn OFF, a strong pull-down strength (e.g., low pull-downresistance) will be provided at the gate input of the low-side FET 1120.This strong pull-down strength (e.g., low pull-down resistance) willcause the low-side FET 1120 to begin switching rapidly to the OFF state.

After the low side FET 1120 is turned OFF (and the high-side FET 1115 isturned ON at approximately the same time, for example, such as withinapproximately 15 nanoseconds (ns) of the low-side FET 1120 being turnedOFF), the voltage at the voltage output 1110 and, thus, at the input1220 will then begin to increase. When the voltage difference betweenthe inputs 1220 and 1224 exceeds the reverse breakdown voltage of theZener diode 1228, the Zener diode 1228 will enter avalanche mode. Oncein avalanche mode, current will flow through the Zener diode 1228 and,thus, through the bias FET 1236. In the illustrate example, the Zenerdiode 1228 and the bias resistors 1232 and 1240 are chosen such that:(1) the Zener diode 1228 will avalanche at a predetermined voltage valueand (2) the voltage at the source of the bias FET 1236 will correspondto a logic HIGH value when the Zener diode 1228 enters avalanche mode.In an example implementation with PVDD 1125 set to 150 volts and PGND1130 set to 0 volts, the Zener diode 1228 and the bias resistors 1232and 1240 are chosen such that: (1) the Zener diode 1228 will avalanchewhen the voltage difference between the inputs 1220 and 1224 is 125volts (e.g., when the voltage at the voltage output 1110 increases by125 volts from the voltage at PGND 1130) and (2) the voltage at thesource of the bias FET 1236 will be substantially equal to the voltageat GVDD 1145 when the Zener diode 1228 enters avalanche mode.

When the Zener diode 1228 enters avalanche mode at the predeterminedvoltage difference between the inputs 1220 and 1224 (or, equivalently,when the voltage at the voltage output 1110 increases a predeterminedamount above the voltage at PGND 1130), the source of the bias FET 1236will be a logic HIGH value. This logic HIGH value is provided to theinput of the inverter 1244 which will, in turn, provide a logic LOWvalue to one input of the AND gate 1248. With one input set to logicLOW, the output of the AND gate 1248 will be a logic LOW, therebyturning OFF the second pull-down FET 1216. The first pull-down FET 1212will still be turned ON by the logic HIGH output of the low-side driver1140. With the first pull-down FET 1212 turned ON and the secondpull-down FET 1216 now turned OFF, a reduced pull-down strength (e.g.,higher pull-down resistance) will be provided at the gate input of thelow-side FET 1120. This reduced pull-down strength (e.g., higherpull-down resistance) will cause a reduction in the voltage spikesobserved at the output of the low-side FET 1120 and, thus, at thevoltage output 1110.

The example implementation of the high-side spike reduction circuit 1165illustrated in FIG. 12 is similar to the example implementation of thelow-side spike reduction circuit 1170. The operation of the examplehigh-side spike reduction circuit 1165 is also similar to the operationof the example low-side spike reduction circuit 1170 in the illustratedexample. For example, the illustrated implementation of the high-sidespike reduction circuit 1165 includes a pull-down circuit 1254 and apull-up FET 1258 similar to the pull-down circuit 1204 and pull-up FET1208 included in the example low-side spike reduction circuit 1170. Likethe pull-down circuit 1204, the pull-down circuit 1254 also includes afirst pull-down FET 1262 and a second pull-down FET 1266 configured toallow the strength of the high-side pull-down circuit 1254 to vary basedon the output voltage sensed at the voltage output 1110. In particular,the first and second pull-down FETs 1262 and 1266 provide a highpull-down strength (e.g., corresponding to a low resistance path to thevoltage output 1110) for the high-side pull-down circuit 1254 when bothFETs are initially turned ON. As discussed above in connection with FIG.11, this high pull-down strength causes the high-side FET 1115 to beginswitching rapidly to the OFF state. Then, at a later time when theoutput voltage 1110 decreases by a predetermined amount, the secondpull-down FET 1266 is turned OFF to reduce the pull-down strength (e.g.,corresponding to a higher resistance path to PGND 1130) for thehigh-side pull-down circuit 1254. As discussed above in connection withFIG. 11, this lower pull-down strength causes a reduction in the voltagespikes observed at the output of the high-side FET 1115 and, thus, atthe voltage output 1110.

Similar to the second pull-down FET 1216 included in the examplelow-side pull-down circuit 1204, the pull-down FET 1266 included in theexample high-side pull-down circuit 1254 is controlled by the remainingcircuitry in the example high-side spike reduction circuit 1165. Likefor the example low-side spike reduction circuit 1170, the examplehigh-side spike reduction circuit 1165 includes inputs 1270 and 1274 tosense the voltage at voltage output 1110 and, in particular, the voltageat the voltage output 1110 relative to the other side of the high-sideFET 1115. In the illustrated example, the input 1270 is electricallycoupled to the cathode of a Zener diode 1278 and the input 1274 iselectrically coupled to the anode of the Zener diode 1278. Similar tothe configuration of the Zener diode 1228 of the example low-side spikereduction circuit 1170, in the example high-side spike reduction circuit1165 the input 1274 is electrically coupled to the anode of the Zenerdiode 1278 through a first bias resistor 1282, a bias transistor 1286and a second bias resistor 1290. Additionally, the source of the biasFET 1286 included in the high-side spike reduction circuit 1165 iscoupled to an inverter 1294 which, in turn, drives an input of an ANDgate 1298, which is also like the illustrated implementation of theexample low-side spike reduction circuit 1170.

Similar to the operation of the example low-side spike reduction circuit1170, when the high-side FET 1115 is initially turned OFF after being inthe ON state, the voltage at the voltage output 1110 and, thus, at theinput 1270 of the example high-side spike reduction circuit 1165 willstill be substantially equal to the voltage at PVDD 1125. Thus, nocurrent will initially flow through the Zener diode 1278 because it willbe only nominally reverse-biased. With no current initially flowingthrough the Zener diode 1278, the source of the bias FET 1286 willprovide a logic LOW value to the input of an inverter 1294 which will,in turn, provide a logic HIGH value to one input of an AND gate 1298.When the logic LOW value is applied to the high-side control input 1155to turn OFF the high side FET 1115, the high-side driver 1135 willprovide a logic HIGH value to the other input of the AND gate 1298. Withboth inputs set to logic HIGH, the output of the AND gate 1298 will be alogic HIGH, thereby turning ON the second pull-down FET 1266. The firstpull-down FET 1262 will also be turned ON by the logic HIGH output ofthe high-side driver 1135. With both pull-down FETs 1262 and 1266initially turned ON when the high-side FET 1115 is initially configuredto turn OFF, a strong pull-down strength (e.g., low pull-downresistance) will be provided at the gate input of the high-side FET1115. This strong pull-down strength (e.g., low pull-down resistance)will cause the high-side FET 1115 to begin switching rapidly to the OFFstate.

After the high-side FET 1115 is turned OFF (and the low-side FET 1120 isturned ON at approximately the same time, for example, such as withinapproximately 15 nanoseconds (ns) of the high-side FET 1115 being turnedOFF), the voltage at the voltage output 1110 and, thus, at the input1274 will then begin to decrease. When the voltage difference betweenthe inputs 1270 and 1274 exceeds the reverse breakdown voltage of theZener diode 1278, the Zener diode 1278 will enter avalanche mode. Oncein avalanche mode, current will flow through the Zener diode 1278 and,thus, through the bias FET 1286. Like for the example low-side spikereduction circuit 1170, the Zener diode 1278 and the bias resistors 1232and 1240 of the illustrated example high-side spike reduction circuit1165 are chosen such that: (1) the Zener diode 1278 will avalanche at apredetermined voltage value and (2) the voltage at the source of thebias FET 1286 will correspond to a logic HIGH value when the Zener diode1278 enters avalanche mode. In an example implementation with PVDD 1125set to 150 volts and PGND 1130 set to 0 volts, the Zener diode 1278 andthe bias resistors 1282 and 1290 are chosen such that: (1) the Zenerdiode 1278 will avalanche when the voltage difference between the inputs1270 and 1274 is 125 volts (e.g., when the voltage at the voltage output1110 decreases by 125 volts from the voltage at PVDD 1125) and (2) thevoltage at the source of the bias FET 1286 will be substantially equalto the voltage at BST 1150 when the Zener diode 1278 enters avalanchemode.

When the Zener diode 1278 enters avalanche mode at the predeterminedvoltage difference between the inputs 1270 and 1274 (or, equivalently,when the voltage at the voltage output 1110 decreases a predeterminedamount below the voltage at PVDD 1125), the source of the bias FET 1286will be a logic HIGH value. This logic HIGH value is provided to theinput of the inverter 1294 which will, in turn, provide a logic LOWvalue to one input of the AND gate 1298. With one input set to logicLOW, the output of the AND gate 1298 will be a logic LOW, therebyturning OFF the second pull-down FET 1266. The first pull-down FET 1262will still be turned ON by the logic HIGH output of the high-side driver1135. With the first pull-down FET 1262 turned ON and the secondpull-down FET 1266 now turned OFF, a reduced pull-down strength (e.g.,higher pull-down resistance) will be provided at the gate input of thehigh-side FET 1115. This reduced pull-down strength (e.g., higherpull-down resistance) will cause a reduction in the voltage spikesobserved at the output of the high-side FET 1115 and, thus, at thevoltage output 1110.

Although the illustrated example implementations of the pull-downcircuits 1204 and 1254 each include a pair of pull-down transistorscoupled in a parallel configuration (e.g., the pull-down transistors1212 and 1216, and the pull-down transistors 1262 and 1266,respectively), other example implementations of the pull-down circuits1204 and/or 1254 could include any number of pull-down transistors. Ingeneral, increasing the number of pull-down transistors used toimplement the pull-down circuits 1204 and/or 1254 (with a correspondingincrease in the complexity of the associated control circuitry,including an increase in the number of Zener diodes 1228 and/or 1278),will increase the granularity of the pull-down strength variationssupported by the corresponding high-side spike reduction circuit 1165and/or low-side spike reduction circuit 1170. Additionally, although theillustrated example implementations of the high-side spike reductioncircuit 1165 and the low-side spike reduction circuit 1170 each includeonly a single pull-up transistor (e.g., the pull-up transistors 1208 and1258), other example implementations of the high-side spike reductioncircuit 1165 and/or the low-side spike reduction circuit 1170 can employpull-up circuits having any number of pull-up transistors. Like theirpull-down counterparts, pull-up circuits having more than one pull-uptransistor are capable of providing variable pull-up strengths tofurther reduce voltage spikes at the output of switching half-bridgeamplifier circuits.

To illustrate an example application of switching half-bridge amplifiersemploying the voltage spike reduction methods and/or apparatus describedherein, a block diagram of an example full-bridge class-D amplifier 1300implemented using two of the example switching half-bridge amplifiercircuits 1100 of FIG. 11 is illustrated in FIG. 13. The two instances ofthe example switching half-bridge amplifier circuit 1100 in FIG. 13 arelabeled 1100A and 1100B for clarity. In the example class-D amplifier1300, the two example switching half-bridge amplifier circuits 1100A and1100B are coupled in a full-bridge output configuration. As such, thevoltage output 1110A of the switching half-bridge amplifier circuit1100A is coupled to one end of an output load 1310 and the voltageoutput 1110B of the switching half-bridge amplifier circuit 1100B iscoupled to the other end of the output load 1310. The output load 1310can be any type of load capable of being driven by a class-D amplifier,such as, for example, a speaker, another audio amplifier, an audio lineinput to an audio device, etc.

In a full-bridge configuration, the switching half-bridge amplifiercircuits 1100A and 1100B are operated in a complimentary, yet opposite,fashion. In particular, in the illustrated example, the switchinghalf-bridge amplifier circuits 1100A and 1100B are configured such thateither: (1) the high-side FET of the switching half-bridge amplifiercircuit 1100A is ON and low-side FET of the switching half-bridgeamplifier circuit 1100B is ON, or (2) the low-side FET of the switchinghalf-bridge amplifier circuit 1100A is ON and the high-side FET of theswitching half-bridge amplifier circuit 1100B is ON. The configurationof the high-side FET of the switching half-bridge amplifier circuit1100A being ON and the low-side FET of the switching half-bridgeamplifier circuit 1100B being ON corresponds to a first voltage phase ofapproximately +PVDD volts across the output load 1310. The configurationof the low-side FET of the switching half-bridge amplifier circuit 1100Abeing ON and the high-side FET of the switching half-bridge amplifiercircuit 1100B being ON corresponds to a second voltage phase ofapproximately −PVDD volts across the output load 1310.

The full-bridge output configuration of the example class-D amplifier1300 is switched between its two output voltage phases of approximately+PVDD volts and approximately −PVDD volts, respectively, according to anelectrical signal to be amplified (e.g., such as an audio signal). Theelectrical signal to be amplified is applied to an amplifier input 1320of the example class-D amplifier 1300. As in a conventional class-Damplifier, the amplifier input 1320 of the example class-D amplifier1300 drives a pulse width modulation (PWM) generator 1330. The examplePWM generator 1330 generates a PWM output signal that includes a streamof pulses having widths that vary as a function of the input signalapplied to the amplifier input 1320. In an example implementation, thePWM generator 1330 generates its PWM output signal by comparing thesignal applied to the amplifier input 1320 with a reference ramp signal.The PWM generator 1330 in this example implementation then outputs alogical HIGH value when the value of the input signal exceeds the valueof the ramp signal and a logical LOW value when the value of the inputsignal does not exceed the value of the ramp signal. The PWM outputsignal, therefore, is a pulse train, wherein the pulse widths representthe periods of time during which the input signal applied to theamplifier input 1320 exceeded the reference ramp signal.

The PWM output signal from the example PWM generator 1330 is applied totwo output driver control circuits 1340A and 1340B that control,respectively, the switching half-bridge amplifier circuits 1100A and1100B. The output driver control circuits 1340A and 1340B are configuredto control the switching half-bridge amplifier circuits 1100A and 1100Bsuch that the full-bridge output is switched to its first output voltagephase of approximately +PVDD volts when the PWM output signalcorresponds to a logic HIGH value, and to its second output voltagephase of approximately—PVDD volts when the PWM output signal correspondsto a logic LOW value.

For example, to switch the full-bridge output to its first outputvoltage phase of approximately +PVDD volts, the output driver controlcircuit 1340A is configured to assert a logic HIGH value at thehigh-side control input 1155A and a logic LOW value at the low-sidecontrol input 1160A to turn ON the high-side FET (and turn OFF thelow-side FET) of the example switching half-bridge amplifier circuit1100A. Furthermore, the output driver control circuit 1340B isconfigured to assert a logic LOW value at the high-side control input1155B and a logic HIGH value at the low-side control input 1160B to turnON the low-side FET (and turn OFF the high-side FET) of the exampleswitching half-bridge amplifier circuit 1100B. Conversely, to switch thefull-bridge output to its second output voltage phase ofapproximately—PVDD volts, the output driver control circuit 1340A isconfigured to assert a logic LOW value at the high-side control input1155A and a logic HIGH value at the low-side control input 1160A to turnON the low-side FET (and turn OFF the high-side FET) of the exampleswitching half-bridge amplifier circuit 1100A. Furthermore, the outputdriver control circuit 1340B is configured to assert a logic HIGH valueat the high-side control input 1155B and a logic LOW value at thelow-side control input 1160B to turn ON the high-side FET (and turn OFFthe low side FET) of the example switching half-bridge amplifier circuit1100B. Because the high-side and low-side FETs of the example switchinghalf-bridge amplifier circuits 1100A and 1100B will continually switchbetween ON states and OFF states according to the PWM pulse streamoutput by the example PWM generator 1330, the example voltage spikereduction circuits included in the switching half-bridge amplifiercircuits 1100A and 1100B will have a tendency to reduce the voltagespikes observed at the output load 1310 relative to a conventionalclass-D amplifier implementation.

Flowcharts representative of example processes that may be implementedby all, or at least portions of, for example, the example switchinghalf-bridge amplifier circuits 1100 and/or 1200, the example high-sidespike reduction circuit 1165, the example low-side spike reductioncircuit 1170, the example low-side pull-down circuit 1204, the examplehigh-side pull-down circuit 1254, and/or the example class-D amplifier1300 are shown in FIGS. 14 and 15. Additionally or alternatively, any,all or portions thereof of the example switching half-bridge amplifiercircuits 1100 and/or 1200, the example high-side spike reduction circuit1165, the example low-side spike reduction circuit 1170, the examplelow-side pull-down circuit 1204, the example high-side pull-down circuit1254, and/or the example class-D amplifier 1300, and/or the exampleprocesses represented by the flowcharts of FIGS. 14 and/or 15 could beimplemented by any combination of software, firmware, hardware devicesand/or combinational logic, other circuitry, etc., such as the hardwarecircuitry and transistors, etc., shown in FIG. 11-13. Furthermore, theprocess represented by each flowchart may be implemented by one or moreprograms comprising machine readable instructions for execution by: (a)a processor, such as the processor 1612 shown in the example system 1600discussed below in connection with FIG. 16, (b) a controller, and/or (c)any other suitable device. The one or more programs may be embodied insoftware stored on a tangible medium such as, for example, a flashmemory, a CD-ROM, a floppy disk, a hard drive, a DVD, or a memoryassociated with the processor 1612, but persons of ordinary skill in theart will readily appreciate that the entire program or programs and/orportions thereof could alternatively be executed by a device other thanthe processor 1612 and/or embodied in firmware or dedicated hardware(e.g., implemented by an application specific integrated circuit (ASIC),a programmable logic device (PLD), a field programmable logic device(FPLD), discrete logic, etc.). Also, some or all of the processesrepresented by the flowcharts of FIGS. 14 and 15 may be implementedmanually. Further, although the example processes are described withreference to the flowcharts illustrated in FIGS. 14 and 15, persons ofordinary skill in the art will readily appreciate that many othertechniques for implementing the example methods and apparatus describedherein may alternatively be used. For example, with reference to theflowcharts illustrated in FIGS. 14 and 15, the order of execution of theblocks may be changed, and/or some of the blocks described may bechanged, eliminated, combined and/or subdivided into multiple blocks.

An example process 1400 that may be implemented by the example low-sidespike reduction circuit 1170 of FIGS. 11 and/or 12 is illustrated inFIG. 14. The example process 1400 may be performed continuously, basedon an occurrence of a predetermined event (e.g., such as when thelow-side control input 1160 is set to a logic LOW value to turn OFF thelow-side FET 1120), etc., or any combination thereof. The exampleprocess 1400 begins execution at block 1410 at which the low-sidecontrol input 1160 of the example low-side spike reduction circuit 1170is set to a logic LOW value to turn OFF the example low-side FET 1120 inthe output stage 1105 of the example switching half-bridge amplifiercircuit 1100 and/or 1200. Control then proceeds to block 1420 at whichthe example low-side spike reduction circuit 1170 is configured toprovide its full pull-down strength to the gate input of the examplelow-side FET 1120 to turn OFF the example low-side FET 1120. Forexample, at block 1420 both the first and second pull-down FETs 1212 and1216 included in the example low-side pull-down circuit 1204 of theexample low-side spike reduction circuit 1170 may be turned ON toprovide a high pull-down strength (e.g., corresponding to a lowresistance path to PGND 1130) to the gate input of the example low-sideFET 1120.

Next, control proceeds to block 1430 at which the inputs 1220 and 1224of the example low-side spike reduction circuit 1170 sense the outputvoltage at the voltage output 1110 of the example switching half-bridgeamplifier circuit 1100 and/or 1200. For example, at block 1430 theinputs of the Zener diode 1228 may be used to sense the voltage at thevoltage output 1110 and, in particular, the voltage at the voltageoutput 1110 relative to the other side of the low-side FET 1120. Controlthen proceeds to block 1440 at which the example low-side spikereduction circuit 1170 determines whether the voltage at the voltageoutput 1110 has increased to a predetermined value. For example, atblock 1440 the voltage at the voltage output 1110 is determined to haveincreased to the predetermined value when the Zener diode 1228 entersavalanche mode. If the voltage at the voltage output 1110 has notincreased to the predetermined value (block 1440), control returns toblock 1430 at which the example low-side spike reduction circuit 1170continues to sense the output voltage at the voltage output 1110.

However, if the voltage at the voltage output 1110 has increased to thepredetermined value (block 1440), control proceeds to block 1450 atwhich the example low-side spike reduction circuit 1170 is configured toreduce its pull-down strength provided to the gate input of the examplelow-side FET 1120. For example, at block 1450 the second pull-down FET1216 included in the example low-side pull-down circuit 1204 of theexample low-side spike reduction circuit 1170 may be turned OFF toreduce the pull-down strength (e.g., increase the pull-down resistance)provided at the gate input of the low-side FET 1120. Execution of theexample process 1400 then ends.

An example process 1500 that may be implemented by the example high-sidespike reduction circuit 1165 of FIGS. 11 and/or 12 is illustrated inFIG. 15. The example process 1500 may be performed continuously, basedon an occurrence of a predetermined event (e.g., such as when thehigh-side control input 1155 is set to a logic LOW value to turn OFF thehigh-side FET 1115), etc., or any combination thereof. The exampleprocess 1500 begins execution at block 1510 at which the high-sidecontrol input 1155 of the example high-side spike reduction circuit 1165is set to a logic LOW value to turn OFF the example high-side FET 1115in the output stage 1105 of the example switching half-bridge amplifiercircuit 1100 and/or 1200. Control then proceeds to block 1520 at whichthe example high-side spike reduction circuit 1165 is configured toprovide its full pull-down strength to the gate input of the examplehigh-side FET 1115 to turn OFF the example high-side FET 1115. Forexample, at block 1520 both the first and second pull-down FETs 1262 and1266 included in the example high-side pull-down circuit 1254 of theexample high-side spike reduction circuit 1165 may be turned ON toprovide a high pull-down strength (e.g., corresponding to a lowresistance path to the voltage output 1110) to the gate input of theexample high-side FET 1115.

Next, control proceeds to block 1530 at which the inputs 1270 and 1274of the example high-side spike reduction circuit 1165 sense the outputvoltage at the voltage output 1110 of the example switching half-bridgeamplifier circuit 1100 and/or 1200. For example, at block 1530 theinputs of the Zener diode 1278 may be used to sense the voltage at thevoltage output 1110 and, in particular, the voltage at the voltageoutput 1110 relative to the other side of the high-side FET 1115.Control then proceeds to block 1540 at which the example high-side spikereduction circuit 1165 determines whether the voltage at the voltageoutput 1110 has decreased to a predetermined value. For example, atblock 1540 the voltage at the voltage output 1110 is determined to havedecreased to the predetermined value when the Zener diode 1278 entersavalanche mode. If the voltage at the voltage output 1110 has notdecreased to the predetermined value (block 1540), control returns toblock 1530 at which the example high-side spike reduction circuit 1165continues to sense the output voltage at the voltage output 1110.

However, if the voltage at the voltage output 1110 has decreased to thepredetermined value (block 1540), control proceeds to block 1550 atwhich the example high-side spike reduction circuit 1165 is configuredto reduce its pull-down strength provided to the gate input of theexample high-side FET 1115. For example, at block 1550 the secondpull-down FET 1266 included in the example high-side pull-down circuit1254 of the example high-side spike reduction circuit 1165 may be turnedOFF to reduce the pull-down strength (e.g., increase the pull-downresistance) provided at the gate input of the high-side FET 1115.Execution of the example process 1500 then ends.

FIG. 16 is a block diagram of an example system 1600 capable ofimplementing the apparatus and methods disclosed herein. The system 1600can be, for example, a server, a personal computer, a personal digitalassistant (PDA), an Internet appliance, a DVD player, a CD player, adigital video recorder, a personal video recorder, a set top box, or anyother type of computing device.

The system 1600 of the instant example includes a processor 1612 such asa general purpose programmable processor. The processor 1612 includes alocal memory 1614, and executes coded instructions 1616 present in thelocal memory 1614 and/or in another memory device. The processor 1612may execute, among other things, machine readable instructions toimplement some or all of the processes represented in FIGS. 14 and/or15. The processor 1612 may be any type of processing unit, such as oneor more microprocessors from the Texas Instruments OMAP® family ofmicroprocessors. Of course, other processors from other families arealso appropriate.

The processor 1612 is in communication with a main memory including avolatile memory 1618 and a non-volatile memory 1620 via a bus 1622. Thevolatile memory 1618 may be implemented by Static Random Access Memory(SRAM), Synchronous Dynamic Random Access Memory (SDRAM), Dynamic RandomAccess Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM) and/orany other type of random access memory device. The non-volatile memory1620 may be implemented by flash memory and/or any other desired type ofmemory device. Access to the main memory 1618, 1620 is typicallycontrolled by a memory controller (not shown).

The system 1600 also includes an interface circuit 1624. The interfacecircuit 1624 may be implemented by any type of interface standard, suchas an Ethernet interface, a universal serial bus (USB), and/or a thirdgeneration input/output (3GIO) interface. In an example implementationof the full-bridge class-D amplifier 1300 based on the example system700, the interface circuit 724 may implement the full-bridge class-Damplifier 1300 to provide an interface between the amplifier input 1320and the output load 1310.

One or more input devices 1626 are connected to the interface circuit1624. The input device(s) 1626 permit a user to enter data and commandsinto the processor 1612. The input device(s) can be implemented by, forexample, a keyboard, a mouse, a touchscreen, a track-pad, a trackball,an isopoint and/or a voice recognition system.

One or more output devices 1628 are also connected to the interfacecircuit 1624. The output devices 1628 can be implemented, for example,by display devices (e.g., a liquid crystal display, a cathode ray tubedisplay (CRT)), by a printer and/or by speakers. The interface circuit1624, thus, typically includes a graphics driver card.

The interface circuit 1624 also includes a communication device such asa modem or network interface card to facilitate exchange of data withexternal computers via a network (e.g., an Ethernet connection, adigital subscriber line (DSL), a telephone line, coaxial cable, acellular telephone system, etc.).

The system 1600 also includes one or more mass storage devices 1630 forstoring software and data. Examples of such mass storage devices 1630include floppy disk drives, hard drive disks, compact disk drives anddigital versatile disk (DVD) drives. The mass storage device 1630 may beused to store machine readable instructions to implement the exampleprocesses 1400 and/or 1500 of FIGS. 14 and 15, respectively.Alternatively, the volatile memory 1618 may be used to store machinereadable instructions to implement the example processes 1400 and/or1500.

As an alternative to implementing the methods and/or apparatus describedherein in a system such as the device of FIG. 16, the methods and orapparatus described herein may be embedded in a structure such as aprocessor and/or an ASIC (application specific integrated circuit).

Additionally, the examples disclosed herein have typically assumedcertain voltage polarities for the operational characteristics of thedevices, components, circuit elements, etc., used to implement theexample methods and apparatus disclosed herein. In these examples,certain positive voltages and/or voltages exceeding a threshold maycause a particular device, component, circuit element, etc., to exhibitone characteristic (e.g., such as turning ON), whereas certainnon-positive (e.g., zero and/or negative) voltages and/or voltages notexceeding a threshold may cause the device, component, circuit element,etc., to exhibit a different characteristic (e.g., such as turning OFF).However, it is readily apparent that the methods and apparatus describedherein can be used in example implementations based on different, oropposite, polarity definitions.

Furthermore, in the examples described herein, methods and apparatus toreduce substrate bounce effects from substrate currents are disclosed.The substrate clamp provides a low impedance path to ground whensubstrate currents are injected into the substrate. As a result,substrate currents do not affect the circuit. Although the examplesdescribed relate to switching amplifiers, persons having ordinary skillin the art will readily appreciate that substrate clamp may beimplemented into any number of electrical circuits to reduce substratecurrents. For example, the substrate clamp may be implemented in powersupplies, mixed-mode integrated circuits, etc.

Finally, although certain example methods, apparatus and articles ofmanufacture have been described herein, the scope of coverage of thispatent is not limited thereto. On the contrary, this patent covers allmethods, apparatus and articles of manufacture fairly falling within thescope of the appended claims either literally or under the doctrine ofequivalents.

1. An apparatus to reduce spike voltages in a switching amplifier, theapparatus comprising: an input to sense an output voltage of theswitching amplifier; and a pull-down circuit to electrically couple theapparatus with a transistor in the switching amplifier, wherein thepull-down circuit is configured to vary in strength based on the outputvoltage sensed by the input.
 2. An apparatus as defined in claim 1wherein the input is electrically coupled to a Zener diode configured toenter an avalanche mode at a predetermined value of the output voltageof the switching amplifier.
 3. An apparatus as defined in claim 2wherein the pull-down circuit is configured to vary in strength when theZener diode enters the avalanche mode.
 4. An apparatus as defined inclaim 1 wherein the pull-down circuit comprise at least two transistors.5. An apparatus as defined in claim 4 wherein operation of at least oneof the transistors is controlled to vary the strength of the pull-downcircuit according to the sensed output voltage of the switchingamplifier.
 6. An apparatus as defined in claim 1 wherein the pull-downcircuit is configured to reduce in strength when the output voltage ofthe switching amplifier sensed by the input reaches a predeterminedvalue.
 7. An apparatus as defined in claim 6 wherein a resistanceassociated with the pull-down circuit is increased to reduce thestrength of the pull-down circuit.
 8. An apparatus as defined in claim 1wherein the pull-down circuit is electrically coupled to a low-sidetransistor of the switching amplifier, and wherein a resistanceassociated with the pull-down circuit is configured to increase when theoutput voltage of the switching amplifier sensed by the input increasesby a predetermined amount after the low-side transistor has been turnedOFF.
 9. An apparatus as defined in claim 1 wherein the pull-down circuitis electrically coupled to a high-side transistor of the switchingamplifier, and wherein a resistance associated with the pull-downcircuit is configured to decrease when the output voltage of theswitching amplifier sensed by the input decreases by a predeterminedamount after the high-side transistor has been turned OFF.
 10. Anapparatus as defined in claim 1 wherein the pull-down circuit isconfigured to vary in strength to reduce voltage spikes in the outputvoltage of the switching amplifier.
 11. An apparatus as defined in claim1 further comprising a pull-up circuit electrically coupled to thetransistor in the switching amplifier, wherein the pull-up circuit isconfigured to vary in strength based on the output voltage sensed by theinput.
 12. A method to reduce spike voltages in a switching amplifier,the method comprising: sensing an output voltage of the switchingamplifier; and modifying a pull-down strength associated with an inputof a transistor in the switching amplifier based on the sensed outputvoltage of the switching amplifier.
 13. A method as defined in claim 12wherein modifying the pull-down strength associated with the input ofthe transistor comprises increasing a resistance coupled to the input ofthe transistor when the sensed output voltage of the switching amplifierreaches a predetermined value.
 14. A method as defined in claim 12wherein the transistor comprises a low-side transistor of the switchingamplifier, and wherein modifying the pull-down strength associated withthe input of the transistor comprises increasing a resistance coupled tothe input of the low-side transistor when the sensed output voltage ofthe switching amplifier increases by a predetermined amount after thelow-side transistor has been turned OFF.
 15. A method as defined inclaim 12 wherein the transistor comprises a high-side transistor of theswitching amplifier, and wherein modifying the pull-down strengthassociated with the input of the transistor comprises increasing aresistance coupled to the input of the high-side transistor when thesensed output voltage of the switching amplifier decreases by apredetermined amount after the high-side transistor has been turned OFF.16. An amplifier comprising: a switching output stage; and a spikereduction circuit electrically coupled to an input corresponding to theswitching output stage, wherein the spike reduction circuit isconfigured to provide a variable pull-down strength to the input basedon an output voltage associated with the switching output stage.
 17. Anamplifier as defined in claim 16 further comprising a driverelectrically coupled by the spike reduction circuit to the inputcorresponding to the switching output stage, and wherein the spikereduction circuit is configured to reduce the pull-down strengthprovided to the input when the output voltage reaches a predeterminedvalue after the driver provides an OFF signal to the input.
 18. Anamplifier as defined in claim 16 wherein the switching output stage is afirst switching output stage, the spike reduction circuit is a firstspike reduction circuit electrically coupled to a first inputcorresponding to the first switching output stage, the variablepull-down strength is a first variable pull-down strength and the outputvoltage is a first output voltage associated with the first switchingoutput stage, and further comprising: a second switching output stageand a second spike reduction circuit electrically coupled to a secondinput corresponding to the second switching output stage, wherein thesecond spike reduction circuit is configured to provide a secondvariable pull-down strength to the second input based on a second outputvoltage associated with the second switching output stage.
 19. Anamplifier as defined in claim 18 wherein the first switching outputstage and the second switching output stage are configured as afull-bridge output.
 20. An amplifier as defined in claim 19 wherein thefirst spike reduction circuit is configured to reduce the firstpull-down strength provided to the first input corresponding to thefirst switching output stage and the second spike reduction circuit isconfigured to reduce the second pull-down strength provided to thesecond input corresponding to the second switching output stage, andwherein the first spike reduction circuit reduces the first pull-downstrength and the second spike reduction circuit reduces the secondpull-down strength during respective opposite voltage phases of thefull-bridge output.
 21. A spike voltage reduction circuit for use in aswitching amplifier, the spike voltage reduction circuit comprising: aZener diode to sense an output voltage of the switching amplifier,wherein the Zener diode is configured to enter an avalanche mode at apredetermined value of the output voltage of the switching amplifier;and a pull-down circuit electrically coupled to an input of anoutput-stage transistor of the switching amplifier, wherein thepull-down circuit comprises a pair of field effect transistorsconfigured to both turn ON to provide a first pull-down resistance tothe input of the output-stage transistor to begin turning theoutput-stage transistor OFF, and wherein one of the pair of field effecttransistors is configured to turn OFF when the Zener diode enters theavalanche mode to provide a second pull-down resistance to the input ofthe output-stage transistor, wherein the second pull-down resistance ishigher than the first pull-down resistance.
 22. A spike voltagereduction circuit as defined in claim 21 wherein the output-stagetransistor is a low-side output-stage transistor and wherein the Zenerdiode is configured to enter the avalanche mode when the output voltageof the switching amplifier increases by a predetermined amount after thepair of field effect transistors have both been turned ON to turn thelow-side output-stage transistor OFF.
 23. A spike voltage reductioncircuit as defined in claim 21 wherein the output-stage transistor is ahigh-side output-stage transistor and wherein the Zener diode isconfigured to enter the avalanche mode when the output voltage of theswitching amplifier decreases by a predetermined amount after the pairof field effect transistors have both been turned ON to turn thehigh-side output-stage transistor OFF.